Parametric Data Study of High-k Gate with Dielectric Pocket(DP) Gate All Around(GAA) FETs
Description
This paper presents the parameteric data study of the High-k Gate stack with Dielectric Pocket(DP) Gate All Around(GAA) FETs. A High K gate stack and dielectric pockets inside the channel have been used as a performance booster in the device. Dielectric pockets reduce the off current, and a high K gate stacking improves the on current. Both are the critical parameter to evaluate a MOSFET.Reduction in off current reduce the power decipation in off state and increment in on current improves the device speed.Parametric data study has been done for on current(Ion), off current(Ioff), DIBL and transconductance.
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DIBL is an important parameter of short channel effects(SCEs) in sub-decameter devices. A smaller value of DIBL tells that device is less affected by SCEs.Sub-threshold swing(SS) is also an important parameter of short channel effects(SCEs) in nanoscale devices. A smaller value of SS tells that device is less affected by SCEs