Dataset for Modelling Gate-Oxide-Short Defects in FinFET 3D Structure and Development of Associated Fault Models for Complex Logic Gates

Published: 29 November 2021| Version 1 | DOI: 10.17632/td5fvxxspp.1
Roya Dibaj


FinFET manufacturing process for 16 nm technology was simulated using the Sentaurus TCAD ‘sprocess’ tool provided by Synopsys. The process was simulated for both the defect-free triangular FinFET as well as the defective FinFET with Gate-Oxide-Short by introducing pinholes in different locations of the gate. FinFET electrical characteristic curves were acquired through simulations with the Sentaurus TCAD ‘sdevice’ tool. Based on the BSIM-CMG local extraction process and the characteristic curves obtained from TCAD, the HSPICE model parameters for NFinFET and PFinFET transistors were extracted. Matlab scripts were used to calculate an initial estimate for the parameters related to the subthreshold slope, threshold voltage, drain-induced-barrier-lowering, and effective-oxide-thickness. The difference currents and capacitances for all pinhole scenarios were modelled as Verilog-A modules to be applied in circuit-level simulations. Circuit-level simulations were performed with the aid of extracted HSPICE model parameters for triangular-fin FinFET and the developed defect models for various pinhole scenarios.



Carleton University