State transition and output table of FSM for QCA serial decimal pipelined processor based on Turing machine (TM) model
Symbol “-“ indicates the “don’t care” value. This table describes the full instruction cycle, which includes four machine cycles (T0 , T1 , T2 , and T3 ). Each machine cycle includes the 1-CLK binary component phase (highlighted in gray) and 4-CLK quinary component phase. The FSM has two inputs: the second operand bit D and scanned square bit S . The code of FSM state is represented by the TM state bit q and axillary carry flag c . The FSM outputs are: the reconfigurable tape control bits WR, SH, FB and carry-out bit CO . The second operand D , 9’s complement control bit CM , and carry-in value C are selected by the code of operation.