Dataset for: Effective Logic Synthesis Flow for Threshold Logic Circuit Design

Published: 27 September 2017| Version 1 | DOI: 10.17632/ypvc8p99cb.1
Contributors:
Augusto Neutzling,
Jody Maick Matos,
Alan Mishchenko,
Andre Reis,
Renato Ribas

Description

This dataset comprises all the necessary data to reproduce the obtained results presented in the manuscript entitled "Effective Logic Synthesis Flow for Threshold Logic Circuit Design".

Files

Steps to reproduce

1) uncompress the tarball 2) open a terminal and run: 2.1) $ source 0-setup-variables.sh 2.2) $ ./1-run.sh [-raoptkKm123456M] Usage: ./1-run [-raoptkKm123456M] -p (re)generate dsdPopulate synthesis -t (re)generate dsdTune synthesis -r (re)generate redundancy synthesis -a (re)generate area synthesis -o (re)generate oriented synthesis -k (re)generate K6 synthesis -K (re)generate K15 synthesis -m (re)generate MtM synthesis -1 (re)compile 'table1-flow' results -2 (re)compile 'table2-redundant' results -3 (re)compile 'table3-area' results -4 (re)compile 'table4-aspac' results -5 (re)compile 'table5-date' results -6 (re)compile 'table6-' results -M (re)compile 'table6MtM' results

Institutions

Universidade Federal do Rio Grande do Sul, University of California Berkeley

Categories

Electronic Design Automation, Nanotechnology, Logic Synthesis

License