Performance analysis of the Junction-less Gate All Around (JL-GAA) MOSFET and Charge Plasma Technique based Junction-less Gate All Around (CPT-JL-GAA) MOSFET on Experimental Data
This paper covers the Performance analysis of the Junctionless Gate All Around (JL-GAA) MOSFET and Charge Plasma Technique based Junctionless Gate All Around (CPT-JL-GAA) MOSFET on Experimental Data. For high-speed ULSI chip design, both are promising solutions. There is no physical junction in both the devices at source to channel and channel to drain Interface. There is no doping concentration gradient for specific regions; therefore, device fabrication becomes easier than the planer MOSFETs. Experimental data for the analog performance of both the devices have been extensively extracted from ATLAS-3D Device Simulator. Analog performance date parameters are also compared. It is found that the Charge Plasma Technique based Junction less Gate All Around (CPT-JL-GAA) MOSFET are better for analog performance in comparison to Junction less Gate All Around (JL-GAA) MOSFET.
Steps to reproduce
Both device parameters like Subthreshold swing, transconductance, Ion/Ioff ratio, Ion Current, Ioff current and Drain Induced Barrier Lowering are measured. These parameters are extracted by simulation of devices using the device simulator software.