SL-BB: Reproducibility Package for a State-Lifetime-Aware Branch-and-Bound FPGA Architecture
Description
This reproducibility package supports the study “SL-BB: A State-Lifetime-Aware Branch-and-Bound FPGA Architecture for High-Throughput Exact Permutation Flow Shop Scheduling.” It contains the source code for the three evaluated FPGA architectures Conventional B&B, Unpipelined SL-BB, and Pipelined SL-BB together with state-lifetime profiling outputs, cycle-accurate RTL transaction results, clean post-route utilization, timing and power reports, and PL-side ZedBoard validation artifacts. The package is organized to distinguish profiling, architectural comparison, physical implementation, and board-validation evidence. The corresponding development repository is maintained on GitHub under the project name SL-BB-PFSP-FPGA.
Files
Steps to reproduce
1. Install Vitis HLS 2021.1 and Vivado 2021.1. The target FPGA device is Xilinx Zynq-7000 XC7Z020 (xc7z020clg484-1) with a 100 MHz (10 ns) target clock. 2. Download the repository package and place the Taillard PFSP benchmark files under data/taillard/ as described in data/README.md. Raw Taillard benchmark files are not redistributed. 3. The three evaluated architectures are provided under src/: conventional/, unpipelined_slbb/, and pipelined_slbb/. 4. From the repository root, run vitis_hls -f scripts/run_hls.tcl to reproduce the final HLS flow. The accompanying testbench and batch script are provided under tb/ and scripts/. 5. Profiling outputs, RTL transaction results, post-route utilization/timing/power reports, and derived energy summaries are provided under results/. The exact workload definitions are documented in EXPERIMENT_CONTRACT.md: 20,000 parent expansions per instance for profiling and 50 parent expansions per instance for the matched RTL architectural comparison. EXPERIMENT_CONTRACT 6. For physical validation, use the files under board_validation/. The representative ZedBoard validation uses Taillard ta001 (20×5), max_parents_popped=50, and completes after 7 parent expansions. The ILA-enabled debug build is separate from the clean implementations used for the manuscript resource, timing, and power results.
Institutions
- Isparta University of Applied SciencesIsparta, Isparta