Supporting Information for "Moiré Self-Aligned Fabrication of Sub-20 nm Ultrashort Channels in Two-Dimensional Devices"
Description
It includes optical images and electrical characteristics of representative long- and short-channel WS2 FETs fabricated by conventional EBL, scaling behavior and TLM-based contact resistance analysis of these devices, output characteristics before thermal annealing, electrical characterization of an additional 30 nm WS2 FET, and demonstration of moiré self-aligned electrode arrays fabricated directly on unetched WS2 flakes.
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Sample Preparation and Fabrication CVD-grown monolayer WS2 was transferred onto 280 nm SiO2/Si substrates utilizing a standard wet-transfer technique. To define the nanoribbon geometry, a positive-tone PMMA A3 resist was spin-coated onto the sample at 1400 rpm, followed by a bake at 180°C for 5 minutes. EBL was then employed to pattern the ribbon structures, operated at an accelerating voltage of 10 keV with an exposure dose of 45 μC/cm2. Subsequently, the unprotected WS2 regions were selectively removed via oxygen (O2) plasma etching. The etching process was conducted with an O2 flow rate of 2 sccm at a power of 2 W for a duration of 15 seconds, successfully defining the isolated WS2 nanoribbons for subsequent electrode integration. Fabrication of Moiré Electrode Arrays To generate the moiré-defined nanogaps, a sequential two-step lithography process was executed. First, a PMMA A3 resist was spin-coated onto the nanoribbon-patterned substrate at 1400 rpm and baked at 180°C for 5 minutes. The first electrode array (period L1 =1.8 μm, contact length = 500 nm) was patterned using a TESCAN EBL system operating at an accelerating voltage of 30 kV with an exposure dose of 115 μC/cm2. To ensure high pattern fidelity and mitigate electron scattering, Proximity Error Correction (PEC) was applied with calculated parameters (α=9, β=641, η=0.8) in "Accurate" exposure mode. Following the first lithographic step, Ni/Au (10/10 nm) electrodes were deposited via electron-beam evaporation under a high vacuum of 5×10−5 Torr, followed by a lift-off process in acetone. Subsequently, the second electrode array (period L2 =1.79 μm, contact length = 500 nm) was fabricated following an identical spin-coating and EBL protocol. The slight spatial period mismatch between the two interlaced arrays resulted in the formation of a moiré pattern with deterministic, sub-lithographic channel lengths. Final Device Integration Upon completion of the moiré electrode fabrication, the sample was inspected via scanning electron microscopy (SEM) to identify and locate target ultrashort channels within the array. A final EBL and metallization step (Ni/Au) was then performed to define the macroscopic electrode pads and interconnects, facilitating subsequent electrical characterization of individual devices. Devices characterization and measurements AFM imaging was performed in tapping mode using a Bruker Dimension Icon microscope. Electrical measurements, including output/transfer characteristics and Schottky barrier analysis, were carried out with an Agilent Technologies B1500 semiconductor parameter analyzer under 1 × 10⁻5 Torr vacuum.