GDSII and OASIS Design Files for the TypeOneBIS Biogenic Replicator — a programmable universal molecular constructor — 2-mer and 16-mer chips v1.01
Description
The designs are governed by the TypeOneBIS Community License (TCL), Zenodo: https://doi.org/10.5281/zenodo.20586399. Layer 4 of each design contains a vectorized copy of the TCL notice. Opening or using the design constitutes acceptance of the TCL in full. The design files are not for fabrication without accepting the TCL. This dataset is a companion to the TypeOneBIS Biogenic Replicator Platform White Paper, Zenodo https://doi.org/10.5281/zenodo.20504143. Presented are OASIS and GDSII Design Files for the TypeOneBIS Biogenic Replicator -- a programmable universal molecular constructor -- that assembles sequence-defined molecules from user provided digital molecular sequence files, using a logarithmic hierarchical merge matrix. This dataset contains the complete mask layouts for two different replicator chips. Both replicator chips are delivered in OASIS (.oas) and GDSII (.gds) formats as semi-flattened layouts. The typeonebis_replicator_layouts_oasis_gds2_v1_01.zip package, SHA256-hash f74528b16374206dd71b771fe9c3a5f10cb04001faf87e8e22f9dc141263f004, includes the layer map, license, warranty disclaimer, README, checksums and alignment mark dimensions. The chips are designed for two-layer PDMS soft lithography using SU-8 3050 photolithography. The input system uses serial PWM loading with a C-section bypass-flush geometry for cleaning and flushing between individual slug (mono-mer or multi-mer) loading. The C-section’s purpose is to provide for low cross-contamination between the loading of successive slug. The 2-mer Baseline Chip. A four (4)-core base replicator chip designed for 4-inch silicon wafers. Each core is independent, and contains two (2) serpentine chambers, which are sequentially loaded via one serial Pulse Width Modulated (PWM) input line. The 2 serpentine chambers constitute the first stage inputs of the hierarchical merge matrix. This replicator-chip can be used to validate the merge matrix, the capillary stop valve diodes, the Quake valve architecture, the PWM serial loading system with C-section bypass-flush, the alignment marks, total internal reflection (TIR), optical nlock/plock addition and nlock/plock ligase reactions, nlock/plock on-off times, etc. The 16-mer Industrial Chip. A two (2)-core replicator chip designed for 6-inch silicon wafers. Each core is independent, and contains sixteen (2 x 8 – input segments) serpentine chambers, which are sequentially loaded via the two (2) serial PWM input line. The 16 serpentine chambers constitute the first stage inputs of the hierarchical merge matrix. This is an industrial replicator chip, intended for production of sequence-defined molecules at scale. The 16-mer replicator is not limited to producing only 16-mers. It is the first rung of a scalable rack based architecture. By using a tree hierarchy layout or daisy-chaining copies of the same chips, the platform scales without bound, and without any change to the chip design. ... see the PDF for more technical details