OpenLane SKY130A Parameter Sweep Dataset: 1,440-Run RTL-to-GDSII Timing, Area, and Power Results
Description
This dataset contains the complete results of a 1,440-run automated parameter sweep of the OpenROAD/OpenLane RTL-to-GDSII flow on the SkyWater 130 nm PDK (SKY130A). Three benchmark designs were evaluated: the SPM 32-bit serial-parallel multiplier, the PicoRV32 RISC-V CPU core, and a custom 4×4 CNN MAC array accelerator (ai_accel). Each design was swept across an 8×5×3×4 Cartesian grid of four configuration parameters: CLOCK_PERIOD (4.0–10.0 ns), FP_CORE_UTIL (35–55%), PL_TARGET_DENSITY (0.4–0.6), and SYNTH_STRATEGY (AREA 0–3), yielding 480 configurations per design. Each row records: design name, run tag, clock period, target frequency (MHz), core utilization, placement density, synthesis strategy, pre-SPEF WNS, post-SPEF WNS, TNS, post-SPEF TNS, core area (µm²), synthesized cell count, critical path delay (ns), internal switching power (µW), switching power (µW), leakage power (µW), and flow status (PASS/FAIL). Tool versions: OpenLane v1.0.2 (commit ff5509f65b17bfa4068d5336495ab1718987ff69), SKY130A PDK (open_pdks hash 0fe599b2afb6708d281543108caf8310912f54af), sky130_fd_sc_hd standard cell library, Ubuntu 24.04 LTS. Associated paper: "Automated Parameter Tuning for Timing Closure in OpenROAD/OpenLane: A Comprehensive Multi-Design Grid Search Framework on the SkyWater 130 nm PDK" — under review. Associated code: https://github.com/alvi-codes/openlane-parameter-sweep
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Institutions
- BRAC UniversityDhaka Division, Dhaka